Digital video correlator



Feb- 28, 1967 J. L. PoTERAcK ETAL 3,307984 DIGITAL VIDEO CORRELATOR Feb. 28, i967 Filed oct. 27. 1964 J. 1 POTERACK ETAL 3,307,184

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DIGITAL VIDEO GORRELATOR 6 Sheets-Sheet I5 Filed Uct. 27, 1964 wwwJDa Hummm 6 Sheets-Sheet 4 J. L.. POTERACK ETAL.

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DXGITAL VIDEO coRRELAToR Filed Oct. 27, 1964 6 Sheets-Sheet 6 www :a @SEF E @053mm imn. .+L v 02.2; 2.52 E E005 w02?. 20000 E E E C 02C MS: 2035002 2 000 1 .w`l Kim 2&52200 .5050 952 E E Emu@ 00.5@ 02.2; 222 J M @xm 002:0 E002 lC y 2 A NEEMSZ. n oizm x 2 1. $0.50 E Iw 0.5500202 -50.20 50500202 m9602200 E. J Kr VL l .DnIO w w. OEmE .mlm Nm `W A QW Alillj m20 m0 J l 2 sv 2 202:20 2 s zl 0.5500202 J 1 mm 1 -55:0 A 000500202 |:H| l IIC M. l .0m .IL mm @MMM mm2 a 2 2 D |rl00m0| 02 ww. m ICI J 1 @Wzwww 1F41 0.6505 c c. j MW /mm AT/ 20w; m20 m2; m m2; 02.0 520002 25mm United States Patent ffice United States of America as represented by the Secretary of the Navy Filed Oct. 27, 1964, Ser. No. 406,947 7 Claims. (Cl. 343--17.1)

This invention rela-tes in general to radar receivers and in particular to radar receivers capable of functioning usefully in the presence of high repetition rate interference and jamming.

One of the problems commonly encountered with radar systems is that of distinguishing target return signals from interference signals. Radar interference generally falls into two categories: random interference land pulsed interference. The random interference, which may be due to receiver noise or atmospheric phenomena, has no ascertainable period of occurrence. The pulsed type of interference, frequently caused by enemy jamming in a military environment, typically has a high repetition rate at or near the repetition rate of the radar system. Although the presence of either type of interference will degrade the operation of a radar system, the presence of pulsed interference of a high repetition rate is especially troublesome to a radar system designed to lock onto and track a particular target. In the case of a visual presentation, such as a PPI scan, the presence of interference can render the identification and selection of the desired target signal difcult or impossible.

It is highly unlikely that .a radar would lock onto land track a pulsed interference signal rather than a true target signal, unless by some small chance the pulsed repetition frequency of both the offending and the offended radars happened to be the same. In such a case, the present invention would not afford any protection against the offending similar pulsed repetition frequency.

However, the pulsed repetition frequency of the pulsed interference would, almost without exception, be different from the pulsed repetition frequency of the protected radar employing the present invention. In this case, then, the correlator forming the invention woud -accomplish the following:

l) The target display would be enhanced in .all modes of operation due to reduction of unsynchronized background pulses.

(2) The time required to lock-on a target is reduced due to enhancement of the displayed target and the reduction of erroneous information that enters the tracking circuitry.

(3) Track gate jitter and antenna jitter is reduced, during the tracking operation, because the amount of errone-I ous information entering the tracking circuitry is reduced.

Another` important feature of the present invention is that it will permit the protected radar to determine its own pulsed repetition frequency and to modulate this frequency in any manner. This feature makes the invention more generally Iuseful than most prior art devices which are restricted to a constant pulsed repetition frequency which they must provide. Many military radars use a rapid pulsed repetition frequency diversity for various reasons and, therefore', cannot tolerate the restriction of a constant frequency imposed by the prior art devices. The digital video correlator making up the present invention was devised to provide the advantages of correlation without the subsequent disadvantages imposed by the prior devices.

According to this invention the problem of interference rejection is approached in the following manner: The period of the radar set is assumed to be divided into N 3,307,184 Patented Feb. 28, 1967 intervals of time. There are N one-bit memory locations corresponding to these N intervals of time. Arrival of one pulse during a particular interval will be recorded in the corresponding memory location. The arrival of additional pulses during the same interval will not have any effect on a memory. A coincidence section will sample the information gathered by the memory section during the preceding period. The presence of information stored in a memory section during the preceding period will cause any video pulse occurring during the interval corresponding to this location to appear at the output.

Accordingly, an object of this invention is to provide a radar receiver that is relatively insensitive to pulsed interference.

Still another object of this invention is the provision of a radar receiver in which the time required to lock onto a target is considerably reduced and also the chance of pulsed interference breaking the tracking of the target is likewise reduced.

Yet another object is to provide a radar receiver in which pulsed interference is removed from the receiver output.

A still further object is the provision of a radar receiver in which the probability of detection of a target in the presence of pulsed interference is improved.

Other objects and advantages of the invention will hereinafter become more fully .apparent from the following description of the annexed drawings which illustrate a preferred embodiment and wherein:

FIG. 1 shows a schematic representation of one embodiment of the invention;

FIG. 2 shows a schematic representation of a circuit which may be used to provide timing pulses for the embodiment of FIG. l;

FIG. 3 shows the timing pulses required for the operad tion of the embodiment of FIG. l;

FIGS. 4a, 4b and 4c show a schematic representation of another embodiment ofthe invention;

FIG. 5 shows a schematic representation of =a circuit which may be used to provide timing pulses for the embodiment of FIGS. 4a, 4b and 4c; and

FIG. 6 shows `the timing pulses required for the operation of the embodiment of FIGS. 4a, 4b and 4c.

Referring now to FIG. l, it will be seen that the invention consists broadly of an input section 10, a memory section 11 and an output section 12. Video signals from the radar receiver are passed through amplier 13, automatic gain 'control 14 and threshold circuit and pulse Shaper 15 whereby the pulses that are delivered to input section 10 are of the correct voltage and width.

Input section 10 includes an input commutator consisting of N flip-flop circuits 16 arranged as a ring counter. Each flip-flop can exhibit one of two voltage conditions at its output, which conditions may be represented, respectively, as a one or a zerof Each of the flip-flops 16 is supplied with clock pulses and with reset pulses whereby the ring counter can be advanced or reset to start position.

The output of each of Hip-flops 16 is connected to one of the inputs of a corresponding coincidence circuit 17. Thus it is seen that there are N coincidence circuits corresponding to the N flip-flops of the input commutator. Each of these coincidence circuits is also provided with an input consisting of video pulses. The output of any of coincidence circuits 17 will be present only upon simultaneous occurrence of a video pulse and an input pulse from a corresponding input commutator position; this output consists of a pulse which is passed on to a corresponding memory section. The presence of an output from one of the coincidence circuits may be considered as a one and the absence of such output as a zero Memoly section 11 contains N-i-2 one-bit memory locations. The memory is a serial shift made up of iiipiiop circuits whereby each memory section can remember either the presence (one) -or the absence (zero of an input signal. Before the start of the next radar system period the information in the memory section is advanced two positions by the receipt of memory shift pulses whereby memory positions 1 and 2 will be cleared to receive new information. That is, the information formerly stored in position 1 is advanced to position 3 and positions l and 2 are reset to zero or no input. The N +2 memory locations are designated on FIG. l as elements 20 to 26.

Output section 12 includes N coincidence circuits 27 each of which receives as an input the information stored in a corresponding one of the memory locations. The first coincidence circuit receives the output from memory location 3 because of the above mentioned two-position memory shift. Each of the coincidence circuits 27 also receives as inputs detected video pulses and a control pulse from an output commutator. This output commutator is a ring counter consisting of N fiip-op circuits, as is the input commutator, and it is reset and pulsed in the same manner as the input commutator by the same pulses. A detected video signal will be passed through a certain one yof coincidence circuits 27 only if that circuit receives at the same time a signal stored in the corresponding memory location and a one signal from lthe corresponding one of output commutator flipflop circuits 30. The outputs of the several coincidence circuits 27 are connected together to form a correlated video output 31 which is passed on to radar system utili- Zation means.

The operation of the embodiment of FIG. 1 will now be explained. As mentioned earlier, the period of the radar track is assumed to be divided into N intervals of time each of duration t. The arrival of a received pulse, whether a desired target return signal or an undesired interference signal, during a particular interval will cause the corresponding memory location to `assume the condition one. That is, the memory location will record the fact of occurrence of at least one received signal during the interval. This will be accomplished in sequence for each of intervals l through N for a given period. In lthe next following period, the arrival of a signal during a given interval is compared with the state of the memory location for that interval. If that memory location contains a one, indicating that a signal had been received during the corresponding interval of the preceding period, then the pulse received during the present period will be passed on to form the correlated video output.

Input commutator functions as a cyclical switch to select in sequence the memory locations ranging from 1 to N. This input commutator, which is made up of N flip-flop circuits arranged as a ring counter, can provide a one output at only one of its positions at any given time. At the beginning of a receiver period the reset pulse shifts the input commutator flip-Hops in parallel to position N whereby only the N fiip-flop has an output. The N posi-tion flip-flop thus exhibits condition one while the rest of the flip-flops exhibit condition zero.7 Upon receipt of the first clock pulse the condition one appears at position 1 of the input commutator and all other positions are zero. Receipt of the second clock pulse causes the condition one to shift to position 2 of the input commutator and so on through the series of N clock pulses.

The time relationship between the reset pulse and the clock pulses can be seen by referring to FIG. 2. The beginning of the radar system period is marked by the receipt from the radar system control oscillator of a timing pulse. As will be explained subsequently, this causes the occurrence of the reset and shift pulses. The

clock pulse sequence begins with the reception of a pulse at the beginning of the radar receiver live-type.

As each of the positions of the input commutator exhibits a one output in sequence the corresponding coincidence circuit 17 is enabled to pass on an output to the corresponding memory position. Thus, as each of the coincidence circuits is actuated in sequence by the input commutator a pulse will be passed on to the corresponding memory circuit if at least one video pulse has also been present during that interval. The information stored in the memory will be advanced two places by the reception of two shift pulses. This clears memory positions 1 and 2 so that any information received during the rst two intervals of this second period can tbe stored in the memory. Because of this memory shift the information previously stored in positions N -l and N of the memory is now stored in memory location N-I-l and N-l-Z, respectively.

Each of the output coincidence circuits 27 has two control inputs and a signal input. A signal applied to the signal input will be passed to the output of the coincidence circuit only if control signals are concurrently present at each of the control inputs. One of these control signals is supplied by the output commutator which functions in the same manner as and in step with the input commutator, previously described. For example, during the first interval, coincidence circuit 1 as so designated in FIG. 1 will receive a control signal from output commutator position 1. Coincidence circuit 1 may also receive from memory position 3 a control signal depending upon whether or not a video pulse was received during the corresponding interval of the preceding period. If such a signal was received, then coincidence circuit 1 will permit passage during the present interval of any video pulses received during this interval of this period. At the end of the first interval the output commutator will be switched by a clock pulse to the second interval whereat the above functions will be repeated. This will be done in sequence for each of the N positions corresponding to the N intervals. It will be seen that in any period there will be a video output only if there is correlation between a video signal received in a given interval and the occurrence of a video signal received during the same interval of the immediately preceding period.

Each of memory positions 3 through N +2 will be reset to zero by a signal received from the corresponding output commutator position l through N. The reset signal for a given interval will occur as the output commutator switches to the next position in the sequence of operation. As mentioned earlier, memory positions 1 and 2 are reset to zero at the beginning of each period.

A circuit for providing the operating pulses shown in FIG. 3 is set forth in FIG. 2. Reception of a signal from the radar system signifying the beginning of the receiver live-time cause bistable multivibrator 32 to gate on a blocking oscillator 33. The output of this oscillator consists of clock pulses having a pulse repetition period of t. The live-time gate is terminated by the reception of a main timing pulse which also signifies the 'beginning of the next period. This main timing pulse is also applied to monostable multivibrator 34. The trailing edge of the output pulse of multivibrator 34 is differentiated in differentiator 35 and inverted in inverter 36. The pulse thus formed triggers monostable multivibrator 37 to provide an output pulse that is supplied to OR gate 40. This OR gate is also directly supplied with the main timing pulses. The two output pulses per period of the OR circuit thus furnish the commutator reset pulse and the memory shift pulses. As shown in FIG. 3, commutator reset and the memory shift occur before the beginning of the first clock pulse.

The basic configuration of this invention has been described with reference to FIG. 1 while FIGS. 4a, 4b and 4c show another embodiment of the invention which requires fewer components. Again the period of the radar set is considered to be divided into N intervals of time for which as described above N-i-Z memory locations are required according to this invention. In the embodiment of FIGS. 4a, 4b and 4c these N +2 memory locations along with their Vassociated input coincidence circuits and output coincidence circuits have been rearranged to form a square matrix having VN-l-Z memory locations per matrix side. This arrangement reduces the number of input and output commutator positions to 2\/'N-{-2 for each of the commutators. Of course, N -|-2 must be a perfect square. For example, if N -l-2 equals 100, the number of commutator flip-flops can be reduced to 20 for each of the input and output commutators.

Each of the matrix segments except as noted below consists of an input coincidence circuit 55, memory position 56 and an output coincidence circuit 57. These components function in the same manner as their counterparts in the embodiment of FIG. 1. No output coincidence circuit is provided for matrix positions 1 and 2, since the memory shift function prevents the reading of any information from these two positions.

The topmost row of the matrix contains memory locations 1 through \/N-{2. The second matrix row will contain memory locations ranging from 1-|-\/N}-2 through 2\/N+2. The remaining matrix rows are similarly arranged, the nal position of the bottommost row containing memory location N-i-2.

The input commutator consists of a top row of ipflop circuits 41, 42, 43 and 44 and a side row of ip-op circuits 4S, 46 and 47. Of course, each of these rows contain \/'N-l2 flip-Hop circuits. Assuming that the input commutator has been reset by an appropriate reset pulse, reception of the first clock pulse causes input position A1, shown by element 41, to exhibit a one output. All of the remaining top row input commutator positions exhibiting a zero output. Reception of further clock pulses will cause the one output to be stepped through input commutator position 2, 3, etc. to position \/N-|2 shown by flip-flop 44. During this phase of the commutator operation the rst of the side row input commutat-or flip-flops 45 has constantly exhibited a one output and the remainder of the side row input commuator flipops have exhibited a zero output. After \/N-|2 clock pulses have been received the one condition of the input commuator top row returns to input position 1 shown again by fiip-fiop 41, and the one condition of the input commuator side row shifts to the second side row position shown by flip-flop 46. Additional clock pulses will cause the second row of the matrix to be scanned by the one condition after which the side row of the input flip-flop will shift to position 3, and so on.

Each of the input coincidence circuits 55 has one input connected to receive detected video pulses and two additional inputs connected to receive, respectively, signals from the top row and the side row of the input comm-utator. There must be coincidence of a one condition received from a flip-flop in each of the top row and side row of the input commutator, in addition to a detected video signal, to effect a memory position. The input commutator thus acts as a modified ring counter to provide selection of each of the memory locations in sequence from location l through location N-i-Z.

Memory shift is accomplished as described with respect to the embodiment of FIG. 1. Immediately prior to the beginning of a new receive period the memory is shifted two locations so that t-he information formerly stored in location 1 now is stored in location 3, thus leaving locations 1 and 2 cleared to receive new information.

The output commutator occupies the remaining two sides of the matrix as shown in FIG. 4. The output commutator consists of a bottom row of ip-flop circuits 50, 51, 52 and 53 and a side row of flip-flop circuits 54, 64 and 65. Each of the bottom and side rows of the output commutator has \/N-|-2 flip-flop circuits. At the beginning of the period the output commutator will be reset by the reset pulse as explained earlier. Since no information is to be read out of the first two matrix positions the bottom row of the output commutator must be shifted to position 3. At the beginning of the period the bottom row of the output commutator will be shifted two positions, after being reset, from position \/Nf2 to position 2. This two-position shift is accomplished by the same pulses which cause the two-position shift of the memory prior to the beginning of the clock pulses. The tirst clock pulse then shifts the bottom row of the output commutator to position 3 whereby flip-flop S2 will exhibit a one output and all other flip-flops on the bottom row will exhibit a Zero output. Subsequent clock pulses will cause the one output of the bottom row to move in sequence to the V'N-i-Z bottom row commutator position. The next clock pulse will cause the bottom row one output to shift back to position 1 and will cause the one output of the side row of the output commutator to shift from its first position, shown by flip-flop 54, to its second position as shown by flip-op 64. It will be seen that the output commutator scans all segments of the matrix excepting the first and second position in a manner similar to that of the input commutator.

Each of the output coincidence circuits 57 has three control inputs and one signal input, the signal input receiving any detected video signals. A given output coincidence circuit, for example that of matrix position 3, is selected by the presence of a one output from an appropriate flip-flop circuit in each of the bottom and side rows of the output commutator. The output coincidence circuit so selected will then permit passage to its output of any detected video signals presented to it at that time only if the presence of a one stored in the corresponding memory location indicates that a video signal had also been received during the corresponding time interval of the immediately preceding period. In this manner, the embodiment of FIG. 4 provides a correlation for each interval -between a video signal detected during that interval and the presence or absence of a detected video signal during the corresponding interval of the last preceding period..

FIG. 6 shows the sequence of timing pulses required for operation of the embodiment of FIG. 4. A main timing pulse is provided by the arrival of the pulse from the radar system control oscillator. This main timing pulse also functions as a reset pulse to reset the nip-Hops of the input and output commutators. Before the beginning of the clock pulses two pulses are applied to the memory and to the -bottorn row of the output commutator to cause a two position shift of each of these units. Reception of a signal indicating the beginning of the receiver live time causes the clock pulse output to begin, and while these can be as many as N clock pulses it should be realized that the radar period can vary and the digital correlator will still function. The radar tells the correlator to start with the live time pulse and to stop With the main timing pulse. The pulse repetition period as shown in FIG. 6 is t.

FIG. 5 shows a circuit which may be used to produce the necessary timing pulses for the embodiment of FIG. 4. Clock pulses are produced with a blocking oscillator 33 controlled lby a bistable multivibrator as described with respect to FIG. 2. Monosta-ble multivibrator 34, differentiator 3S, inverter 36, and monostable multivibrator 37 also function as described in FIG. 2. Additionally, so that the two pulses required for memory and output commutator shift may be produced, the output pulse from monostable multivibrator 37 is supplied to another monostable multivibrator 60 which produces an output of relatively long duration whose trailing edge is differentiated in diierentiator 61. The output pulse of differentiator 61 is inverted by inverter 62 and this inverted pulse triggers monostable multivibrator 63. The output of monostable multivibrator 63, which is a pulse of the same height and duration as the pulse output of multivibrator 37, is passed to OR gate 40.

Each of the circuits of FIG. l and FIG. 4 described above effectively eliminates a high percentage of external interference and internal noise `for the following reasons: The desired pulses representing7 some target object will occu-i at approximately the same range each period and should, therefore, occupy the same memory location each period; there will be coincidence as described above and all target pulses will appear at the output. Interference pulses and noise pulses do not represent the same ranges each period and they, therefore, may or may not occur during corresponding intervals from period to period; the probability of an interference pulse occurring at the output thus is low.

It should lbe understood, of course, that the foregoing disclosure relates to only the preferred embodiments of the invention and that numerous modifications or alterations may be made therein without departing from the spirit and scope of the invention as set forth in the appended claims.

What is claimed is:

1. In a radar receiver the improvement comprising:

timin-g means defining a number N of consecutive and sequential intervals for each period of operation of the receiver;

a memory means having at least N positions;

input means actuated by the timing means, said input means serving to render receptive to the presence of an input signal a separate one of the sto-rage means positions for each of the N intervals whereby for each interval in sequence there is recorded in a corresponding position of the storage means the presence or absence of an input signal occurring during that interval;

output means actuated by the timing means in synchronization with said input means, said output means receiving the input signal and functioning to permit passage to the receiver output of any input signal occurring during an interval of a period only if the presence of an input signal for the corresponding interval of the last preceding period is shown by 'a signal from the appropriate position of the storage means.

2. In a radar receiver the improvement comprising:

timing means defining a number N of consecutive and sequential intervals for each period of operation of the receiver;

memory means containing a number of locations in excess of N, each location being capable of assuming either a first state corresponding to the absence of an input signal or a second state corresponding to the presence of an input signal, the output of each location being a function of its state;

input coincidence means for each of N locations, each of the input coincidence means receiving video signals detected by the receiver and being capable of furnishing to its corresponding memory location an output `signal indicative of the presence of a detected video signal;

input switching means connected to and controlling each of the input coincidence means, the input switching means enabling each one of the input coincidence means, in sequence and consecutively, to furnish to its corresponding memory location a signal indicative of the presence of a detected video signal, the operation of the input switching means being responsive to the timing means;

output coincidence means for each of N memory locations, each of the output coincidence means receiving a detected video signal and receiving the output from the corresponding memory location and being capable of passing a Video signal only in the presence of an output from this corresponding memory location; and

output switching means connected to and controlling each of the output -coincidence means, the output lswitching means enabling each one of the output coincidence means, in sequence and consecutively, to pass to the receiver output any video signal present concurrently with the output from the appropriate memory location.

3. The invention as in claim 2, wherein the output signal of the input coincidence means that is the first in the sequence of operation is supplied to a first memory location, and the output signal of the coincidence means that is the last in the sequence of operation receives the output of a last memory location, whereby there is provided at least one memory location having no corresponding output coincidence means and at least one other memory location having no corresponding input coincidence means, and wherein the memory means is capable of undergoing at least one serial shift in which each memory location excepting the first such location assumes the state of the immediate preceding memory location land in which the first memory location assumes a first state, whereby information in the memory means relating to a period of receiver operation is shifted to enable an insertion into the memory means of information relating at least to the rst interval of the next subsequent interval.

4. The invention as in claim 3 wherein at the start of a receive period, the memory means undergoes serial shifts equal in number to the number of memory locations in excess of N, and wherein each memory location is reset to the first state by a pulse from the output switching means when the output switching means switches control from the output coincidence means corresponding to that memory location to the output coincidence means corresponding to the next memory location.

5. The invention of claim 3, wherein the input switching means includes N flip-flops arranged to form a first ring counter and the output switching means includes N fiipflops arranged to form a second ring counter, each ring counter being capable of exhibiting a control pulse output at only one at a time of its flip-hops, the output of each of the input switching means flip-fiops being received by a corresponding one of the input coincidence means, the output of each of the output switching means flip-flops being received by a corresponding one of the output coincidence means, each of the flip-Hops of both ring counters receiving as outputs from the timing means a reset pulse at the beginning of a period of operation, to enable each ring counter to be reset so that the Nth fiip-fiop of each ring counter exhibits a control pulse output, and one clock pulse corresponding to each interval of a period of operation to enable both ring counters to exhibit an output pulse in sequence and in synchronization from the first flip-flops through the Nth flip-flops, whereby the input coincidence means and output coincidence means are enabled to control the iiow of signals to and from the locations of the memory means.

6. The invention as in claim 3 wherein the memory locations 'and their associated input coincidence means and output coincidence means are arranged to form a square matrix, the input switching means being disposed along two transverse sides of the matrix and the output switching means being disposed along the remaining two sides of ythe matrix.

7. The invention as in claim 6 wherein there are M memory locations in excess of N, whereby the total number of memory locations equals N -l-M, and the square matrix has \/N|M rows of memory locations and their associated input coincidence circuits and loutput coincidence circuits on a side, the input switching means includes ZVN-I-M fiip-flops disposed to form two groups of \/N-l-M flip-flops per group, both groups comprising a ring counter, each ilip-iiop in the rst group corresponding to a row of a first side of the matrix and each iiip-op in the seocnd group corresponding to a roW of a second side of the matrix transverse to the iirst side, the output of each ip-op of both groups being received by all of the input coincidence means contained in the matrix row to which that Hip-flop corresponds, whereby each input coincidence means receives a Hip-flop output from each of the first and second groups, each of the two groups of flip-Hops being capable of exhibiting a control pulse output at only one at a Itime of the Hip-flops in the group, both groups of flip-Hops receiving as an output from the timing means a reset pulse at the beginning of a period of operation to enable each group of Hip-flops to be reset so that the \/N-|M flip-flop in each group will exhibit a control pulse output, the rst group of flip-flops receiving as an output from the timing means one clock pulse corresponding to each interval of a period, and the second group of flipiiops also receiving an output from the \/N|M Hip-flop of the first group, so that the output pulse from the rst group as controlled by the clock pulses will occur in sequence from the rst flip-flop to the \/Nl-M iiip-flop and will then return to the first flip-flop to reset the sequence, and :the output pulse of the second group as controlled by the output received from the rst group Iwill occur in sequence from the first iiip-flop to the VN-l-M flip-flop, the output pulse of the second group advancing to the next flip-flop of that group in sequence upon completion of the \/N-l-M output pulse from the iirst group; the output switching means including 2\/N+M Hip-flops disposed to form a third group and a fourth group e'ach having \/Nl-M flip-flops which comprise a second ring counter, each flip-flop in the third group corresponding to a row of said rst side of the matrix and each flip-flop of the fourth group corresponding to a row of said second side of the matrix, the output of each ilip-iiop of both of the third and fourth groups being received by all of the output coingidence means contained in the matrix row to which that flip-flop corresponds whereby each output coincidence means receives a flip-flop output from each of the third and fourth groups, each of the third and fourth groups of ip-ops being capable of exhibiting a control pulse output at only one at a time of the flip-Hops in the group, both of the third and fourth groups receiving as an output from the timing means the reset pulse at the beginning 0f a period of operation to enable each group of iiip-ops to be reset so that the VN-i-M flip-flops in each group will exhibit a control pulse output, the flip-flops of the rst and third groups in sequence from the first flip-flop to the \/Nf-M flip-flop in each group corresponding to the same matrix row and the flip-Hops of the second yand fourth groups in sequence from the iirst flip-flop to the VN-i-M flip-flop in each group corresponding to the same matrix row, the third group of flip-flops receiving as another output from the timing means M shift pulses and then a clock pulse corresponding to each interval of a period, the fourth group of Hip-Hops receiving an output from the \/N{-M flip-flop of the third group, so that the output pulse from the third group as controlled by the shift and clock pulses Will occur in sequence from the iirst flip-flop to the VN-l-M ip-op and Will then return to the first flip-flop to repeat the sequence and the output pulse of the fourth group as controlled by the output received from the third group Will occur in sequence from the iirst Hip-flop to the \/N+M flip-flop, the output pulse of the fourth group advancing to the next flip-flop of that group in sequence upon completion of the \/N{M output pulses from the third group.

References Cited by the Examiner UNITED sTATEs PATENTS 2,412,974 12/1946 Deloraine.

CHESTER L. IUSTUS, Primary Examiner. RODNEY D. BENNETT, Examiner, 

1. IN A RADAR RECEIVER THE IMPROVEMENT COMPRISING: TIMING MEANS DEFINING A NUMBER N OF CONSECUTIVE AND SEQUENTIAL INTERVALS FOR EACH PERIOD OF OPERATION OF THE RECEIVER; A MEMORY MEANS HAVING AT LEAST N POSITIONS; INPUT MEANS ACTUATED BY THE TIMING MEANS, SAID INPUT MEANS SERVING TO RENDER RECEPTIVE TO THE PRESENCE OF AN INPUT SIGNAL A SEPARATE ONE OF THE STORAGE MEANS POSITIONS FOR EACH OF THE N INTERVALS WHEREBY FOR EACH INTERVAL IN SEQUENCE THERE IS RECORDED IN A CORRESPONDING POSITION OF THE STORAGE MEANS THE PRESENCE OR ABSENCE OF AN INPUT SIGNAL OCCURRING DURING THAT INTERVAL; OUTPUT MEANS ACTUATED BY THE TIMING MEANS IN SYNCHRONIZATION WITH SAID INPUT MEANS, SAID OUTPUT MEANS RECEIVING THE INPUT SIGNAL AND FUNCTIONING TO PERMIT PASSAGE TO THE RECEIVER OUTPUT OF ANY INPUT SIGNAL OCCURRING DURING AN INTERVAL OF A PERIOD ONLY IF THE PRESENCE OF AN INPUT SIGNAL FOR THE CORRESPONDING INTERVAL OF THE LAST PRECEDING PERIOD IS SHOWN BY A SIGNAL FROM THE APPROPRIAWTE POSITION OF THE STORAGE MEANS. 